1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits including transistors and/or other circuit elements including a stress-creating material.
2. Description of the Related Art
Integrated circuits include a large number of circuit elements which include, in particular, field effect transistors. In a field effect transistor, a gate electrode may be separated from a channel region by a gate insulation layer that provides an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are formed.
The channel region, the source region and the drain region may be formed in a semiconductor material, wherein the doping of the channel region is different from the doping of the source region and the drain region. Thus, there is a transition between differently doped semiconductor materials, for example, a PN transition, or a transition between P- or N-doped semiconductor material and substantially undoped semiconductor material, between the source region and the channel region, and between the channel region and the drain region.
In N-type transistors, the source and drain regions are doped with an N-type dopant, and the channel region may be P-doped or substantially undoped. In P-type transistors, the source and drain regions are P-doped, and the channel region may be N-doped or substantially undoped.
Depending on an electric voltage applied between the gate electrode and the source region, the field effect transistor can be switched between an on-state, wherein there is a relatively high electrical conductance between the source region and the drain region, and an off-state, wherein there is a relatively low electrical conductance between the source region and the drain region. The conductance of the channel region in the on-state of the field effect transistor may depend on the dopant concentration in the channel region, the mobility of charge carriers in the channel region, the extension of the channel region in the width direction of the transistor and on the distance between the source region and the drain region, which is commonly denoted as “channel length.”
For increasing the conductance of the channel region in the on-state of the transistor, it has been proposed to improve the mobility of charge carriers in the channel region by modifying the lattice structure of the semiconductor material wherein the channel region is formed. This may be done by creating a tensile or compressive stress in the channel region. A compressive stress in the channel region can increase the mobility of holes, leading to an increase of the conductivity of the channel region of P-type transistors. Conversely, a tensile stress in the channel region can increase the mobility of electrons, which can improve the conductivity of the channel region of N-type transistors.
For providing the stress in the channel region, a material layer having an intrinsic stress may be formed over the transistor. The material layer may include, for example, silicon nitride, and may be formed, for example, by means of a plasma enhanced chemical vapor deposition process. Depending on the parameters of the plasma enhanced chemical vapor deposition process, such as, for example, composition, pressure and/or temperature of a reactant gas, a power of a radio frequency electric discharge created in the reactant gas and/or a bias voltage applied to a substrate on which the transistor is provided, a tensile or compressive intrinsic stress of the material layer may be provided. Moreover, a strength of the tensile or compressive intrinsic stress may be controlled by varying the parameters of the plasma enhanced deposition process.
However, the stress in the channel region of the transistor created by conventional material layers having an intrinsic stress typically is substantially constant after the deposition of the material layer and cannot be adjusted afterwards. Therefore, the performance of the transistor, in particular, the electrical conductance of the channel region in the on-state of the transistor, which is linked to the stress in the channel region provided by the intrinsically stressed material layer, is substantially constant as well.
In view of the situation described above, the present disclosure provides techniques that allow providing a stress in a channel region of a transistor that can be modified after the manufacturing of the transistor.
The present disclosure further provides techniques that allow varying the resistance of a semiconductor region in a circuit element other than a transistor by modifying a stress in the semiconductor region.